Assessment and OS-Level Mitigation of Timing Channels. K. Falkner and Y. Yarom, NICTA CRP ($232,167) (2014-2015)
DIG will be working with Professor Gernot Heiser’s team at NICTA/UNSW on a new collaborative project exploring timing channels and side channels on modern architectures. Led at Adelaide by Yuval Yarom, this project will explore the design and implementation of minimal, low-overhead mechanisms for the seL4 microkernel to support new mitigation strategies for these channels. It will design, and implement minimal, low-overhead mechanisms for the seL4 microkernel that allow mitigation of those channels, and will analyse their effectiveness, in close collaboration with existing SSRG activities on covert information flow.